Reconfigurable Logic for Low - Power Space Systems by Jeffrey

Date The final copy of this thesis has been examined by the signatories, and we find that both the content and the form meet acceptable presentation standards of scholarly work in the above mentioned discipline. Thesis directed by Prof. Dirk Grunwald This research investigates a reconfigurable processing approach to a signal processing application that runs on an onboard space system. The reconfigurable processor is used as an accelerator to the current microprocessor-based system. The algorithms targeted for acceleration are part of a suite of signal processing applications used for detecting ionospheric events. This paper describes the hardware design, implementation and power/performance testing of two different floating point algorithms used in the space system. While the current microprocessor-based hardware running on the onboard space system runs efficiently, this research investigates the potential for energy and performance improvements by using reconfigurable hardware in conjunction with microprocessors.